High-Speed Digital PCB Layout Engineer (m/f/div.)

About this role

The High-Speed Digital PCB Layout Engineer is responsible for the physical realization of complex, multi-layer printed circuit boards, used in advanced products such as video cameras, professional audio systems, embedded AI devices, advanced industrial systems, aerospace applications and MedTech electronics, where signal integrity, timing, and power delivery are the primary design constraints. Responsibilities: Advanced Signal Integrity (SI) Management You will be responsible for ensuring that digital signals reach their destination without distortion, reflections, or excessive noise.

Impedance Control: Calculate and implement controlled impedance for single-ended and differential signals based on dielectric materials and stackup. Length & Phase Matching: Execute precise delay tuning and "snake" routing for high-speed buses (DDR4/5, PCIe Gen 4/5, USB4) to meet strict setup and hold time requirements. Topology Execution: Implement complex routing topologies including Fly-by, T-topology, and Point-to-Point for multi-drop memory interfaces.

Physical Design & Stackup Architecture Designing the "backbone" of the hardware to support high-density interconnects (HDI). Stackup Definition: Collaborate with fabrication houses to define layer counts, copper weights, and specialized materials (e.g., Megtron 6, Rogers) to minimize insertion loss. Constraint Management: Set up and manage thousands of high-speed design rules within the EDA constraint manager to automate error checking.

Micro-Via Strategy: Utilize stacked and staggered micro-vias, blind/buried vias, and via-in-pad technology for 0.4mm and 0.5mm pitch BGA components. Power Integrity (PI) & Thermal Design Ensuring the Power Delivery Network (PDN) can handle high-current transients without excessive voltage drop. Plane Design: Design solid, low-inductance power and ground planes to provide stable voltage to CPUs, FPGAs, and ASICs. Decoupling Optimization: Optimize the placement of decoupling capacitors to minimize the loop inductance of the PDN.

Thermal Relief: Work with mechanical engineers to place high-power components and thermal vias to prevent localized "hot spots" on the board. Qualifications MSc or PhD in Electrical Engineering, Electronics Engineering. 5+ years of experience in electronic hardware design, with a strong focus on high-speed digital circuits. Experience in circuit simulation tools is highly valued. Strong understanding of signal integrity and power integrity concepts.